1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory having a floating gate and a control gate such as an EPROM (Erasable and Programmable ROM) and an E.sup.2 PROM (Electrically Erasable and Programmable ROM).
2. Description of the Related Art
FIG. 8 shows a conventional non-volatile semiconductor memory, for example, an ultraviolet erasable EPROM. FIG. 9 shows a cross sectional structure of FIG. 8.
In the drawing, in a P-type substrate 21, there are formed N type diffusion layers 22 and 23. An an insulating film (not shown) is formed on the P-type substrate 21. A first layer made of polysilicon is a floating gate FG. A second layer made of polysilicon is a control gate CG serving as both an electrode and an access gate to a cell. In this case, both distances d1 and d2 as shown in FIG. 8 are several hundreds .mu.m.
In a case where data is written to the non-volatile semiconductor memory, high voltage of 12.5 V is applied to the control gate CG (word line WL) of the transistor, and at the same time high voltage of about 8 V is supplied to a drain electrode (bit line BL). Then, a hot electron is generated in a channel region, which is in a pinch off state, and this is caught by the floating gate FG. In this type of non-volatile semiconductor, it is desirable that the shift of threshold voltage be large under a condition that the applied voltage is low and the writing time is short.
On the other hand, data retaining characteristic is also important when data writing or reading is not operated, or the reading is operated. It is required that these opposed operations be conformed to a certain characteristic to obtain high reliance.
Moreover, if stored data is read out, the conventional non-volatile semiconductor memory of FIG. 9 is operated by a single power source of 5 V. More specifically, if the control gate CG is selected, a voltage, which is C2/(C1+C2) times the voltage supplied to the control gate CG, is applied to the floating gate FG. C1 is a capacitor, which is between a substrate 21 and the floating gate FG, and C2 is a capacitor, which is between the floating gate FG and the control gate CG. In this state, the shift of the threshold value before or after writing is sensed and amplified by a sense amplifier (not shown). In order to erase the written data, an ultraviolet ray is radiated to the floating gate FG, the electron is excited to be high energy, thereby discharging the electron from the floating gate FG. It is characterized that bits of the ultraviolet erasable EPROM is erased at the same time.
The conventional volatile semiconductor memory has a strong relation with the amount of writing and the reading current. Due to this, in a case where the amount of writing hot electrons varies, the reading speed varies, thereby making it difficult for the speed of the volatile semiconductor memory to be higher.
Moreover, if the hot electrons are written in the floating gate many times, the shift of the threshold values reduces, and endurance deteriorates. Due to this, there occur problems in which the number of times of data writing decreases and reliance lowers. Particularly, if the memory cell is made hyperfine or the voltage is lowered, there are needed a high boosting voltage, a long writing time, and a thin gate oxide film in order to reserve the amount of hot electrons to be injected to the floating gate in the data writing operation. In this case, the above-mentioned problems are more serious.